Improvements in Test Access Design and Scheduling for Checking Chip Manufacturing Quality

Abstract

The use of 3-dimensional (3D) and network-on-chip (NOC) integrated circuits enables more functionality on chip, but they pose challenges for testing for manufacturing defects. Machine learning applications for artificial intelligence need to be highly reliable and so mandate in-system testing.  All of these modern system-on-chip (SOC) devices manufactured using advanced process nodes integrate numerous heterogeneous embedded intellectual property (IP) cores, which require post-fabrication verification. To maintain practical testing procedures, a modular strategy is employed that enables each core to be exercised without revealing its internal structure, thereby facilitating straightforward test-pattern reuse. The primary challenge is the limited scan-in and scan-out bandwidth at the chip boundary, which is significantly lower than the aggregate channel demand of all cores. Further, enabling in-system and system-level tests, the use of functional pins instead of traditional test-only pins is required. Scan-compression techniques, such as Embedded Deterministic Test (EDT), reduce pattern volume but introduce additional complexity in bandwidth allocation. Consequently, an effective Test Access Mechanism (TAM) must address this disparity. Researchers have introduced various TAM architectures that balance wiring overhead, concurrency, compression efficiency, and scheduling complexity. This paper presents a survey of these TAMs, spanning the years and including recent ones. The goal of the paper is to compare several prominent approaches, examining strategies for dividing available TAM width, mapping cores to these divisions, jointly optimizing EDT parameters, and ultimately minimizing total test time while maintaining high fault coverage under realistic bandwidth constraints. It highlights challenges in their implementation and provides direction for further research on TAMs.